In recent years, there has been a request for the of a receiver which supports a plurality of radio communication schemes (hereinafter called the “multi-mode supporting receiver”). For configuring this receiver, channel selection filter circuits are required to support the respective communication schemes. Then, this filter is required to have a function of varying a pass band width over a wide range. Generally, when a receiver is implemented in one chip, a so-called gm-C scheme, which is composed of a gm amplifier and capacitance C, is used as a channel selection filter. The gm amplifier must be provided with a conversion gain over a wide range in order to have a function of variable characteristics in the pass band width.
Specifically, the gm amplifier comprises an active element such as a bipolar transistor, a MOS transistor and the like. In an actual design, a mutual conductance value (hereinafter called the “Gm value”) is often made electrically controllable between −30% and +30% with respect to a design value in order to deal with process variations. A switching system using a switch circuit is generally used for making adjustments beyond that range.
FIGS. 1A, 1B are circuit diagrams illustrating a first prior art example (see IEEE JSSC vol. 37, no. 2, pp. 125-136, February 2002). FIG. 1A is a circuit diagram illustrating the general configuration. FIG. 1B is a circuit diagram illustrating the internal configuration of programmable current mirror circuit G1 or G2 (11 or 12) in FIG. 1A. In FIGS. 1A, 1B, Q330, Q340, Q350, Q360 are p-type MOS transistors; Q370, Q380, Q390, Q400, Q410, Q420, Q430, Q440, Q450, Q460 are n-type MOS transistors, CS400, CS500, CS600 are current sources; V1 is a voltage source; and SW500, SW600, SW700 are switch circuits. Output current signal Iout is supplied from n-type MOS transistors Q410, Q420, Q430 which are arranged in parallel. N-type MOS transistors Q410, Q420, Q430 are configured to be selected by switch circuits SW500, SW600, SW700, respectively.
As differential input voltage signal Vin+ is applied to gate terminals of MOS transistors Q330 and Q340, and another differential input voltage signal Vin− is applied to gate terminals of MOSS transistors Q350 and Q360, the four MOS transistors supply two programmable current mirror circuits G1 and G2 with a current which has a differential component corresponding to the differential input voltages. By switching switch circuits SW500, SW600, SW700, programmable current mirror circuits G1 and G2 can amplify the current having the differential component by a desired factor to deliver output current signal Iout.
In current mirror circuits G1 and G2 illustrated in FIGS. 1A, 1B, switch circuits SW500 and SW600 are connected to a supply voltage side, and n-type MOS transistors Q410 and Q420 are in an operative state. For reducing the Gm value from this state, switch circuit SW600 must be switched to a ground side. In this way, n-type MOS transistor Q420 is brought into an inoperative state, causing the Gm value to decrease. For increasing the Gm value from the illustrated state, switch circuit SW700 must be switched to the supply voltage side. In this way, n-type MOS transistor Q430 is brought into an operative state, causing the Gm value to increase. One feature of this current mirror circuit lies in that one end of the switch circuit is connected to the gate terminal of the MOS transistor, thus reducing the influence of parasitic components (of resistive and capacitive components) of the switch circuit. The current mirror circuit also has a feature that the Gm value can be varied over a wider width as a larger number of MOS transistors are connected in parallel.
FIG. 2 is a circuit diagram illustrating a second prior art example (see Proc. ESSCIRC 2002, pp. 647-650, 2002).
The second prior art example includes n-type MOS transistors Q100 and Q400, p-type MOS transistors Q200 and Q300, and regulated current source CS200. P-type MOS transistors Q200 and Q300 have size parameters set equal to each other. N-type MOS transistor Q100 operates in a triode region, and generates current signal Ids in accordance with the following equation when input voltage signal Vin is applied to a gate terminal:
                    [                  Equation          ⁢                                          ⁢          1                ]                                                                      I          ds                =                  β          ·                      (                                          V                gs                            -                              V                th                            -                                                1                  2                                ⁢                                  V                  ds                                                      )                    ·                      V            ds                                              (        1        )            
A Gm value in turn is given by the following equation by differentiating both sides of Equation (1) with Vgs:
[Equation 2]Gm=β·Vds  (2)where β is a constant, Vth is a threshold, Vgs is a gate-source voltage, and Vds is a drain-source voltage. Vin in FIG. 2 corresponds to gate-source voltage Vgs in Equation (1), and potential VN100 at node N100 corresponds to drain-source voltage Vds.
When control voltage Vt100 is applied to the gate terminal of n-type MOS transistor Q400 which is in a saturation region, current Ids in accordance with the following equation, flows between the drain and source of n-type MOS transistor Q400:
                    [                  Equation          ⁢                                          ⁢          3                ]                                                                      I          ds                =                              β            2                    ⁢                                    (                                                V                  tune                                -                                  V                  N                                -                                  V                  th                                            )                        2                                              (        3        )            where Vtune is Vt100, VN is potential VN 100 which is the potential at node N100, and Vth is a threshold for n-type MOS transistor Q400. Since Ids is a current supplied from regulated current source CS200, potential VN100 is uniquely determined from Equation (3). As a gate voltage of n-type MOS transistor Q100 fluctuates to cause potential VN100 to increase to a higher potential, the gate-source voltage of n-type MOS transistor Q400 is reduced, thus causing potential VN200 at node N200 to increase. Since potential VN200 is a gate voltage of p-type MOS transistor Q200, potential VN100 is drawn back from the higher potential to a lower potential by the inversion amplification action of p-type MOS transistor Q200.
Conversely, when potential VN100 decreases to a lower potential, a similar principle acts in reverse, so that potential VN100 is drawn back from the lower potential to a higher potential. Eventually, VN, which is potential VN100, is fixed at a value determined from Equation (3) and Vt100 which is Vtune. In other words, Vds in Equation (2) is fixed with respect to a gate input voltage of n-type MOS transistor Q100. Therefore, n-type MOS transistor Q100 exhibits a highly linear voltage/current conversion characteristic. Also, since potential VN100 can be adjusted by control voltage Vt100, the Gm value of n-type MOS transistor Q100 can be adjusted in accordance with Equation (2) in which potential VN100 is substituted into source-drain voltage Vds.
In a state where potential VN100 is fixed, a voltage signal applied to the gate of n-type MOS transistor Q100 is converted to the current signal of n-type MOS transistor Q100 based on Equation (1). The current signal of n-type MOS transistor Q100 is converted to voltage signal VN200 at node N200 within a feedback circuit composed of p-type MOS transistors Q200 and Q400, and then is delivered as current signal Iout of p-type MOS transistor Q300. Since p-type MOS transistors Q200 and Q300 are equal in parameter sizes, the current signal of n-type MOS transistor Q100 is equal to Iout. Thus, the voltage/current conversion characteristic of this prior art example is equal to the voltage/current conversion characteristic of n-type MOS transistor Q100, and has high linearity. Also, since the Gm value of n-type MOS transistor Q100 can be adjusted by control voltage Vt100, the Gm value of this prior art example can also be adjusted by Vt100.
Further, since this prior art example comprises only two or three MOS transistors arranged between the power supply and ground, a sufficient bias voltage can be applied to each MOS transistor even with a low voltage power supply. For this reason, this circuit provides a large input dynamic range.
However, the foregoing first prior art example and second prior art example imply the following problems.
In the first prior art example, the gm amplifier can be provided with a wide gain variable range. However, since a switch circuit must be used, a digital circuit is required for controlling the switch circuit, resulting in a complicated circuit configuration in which the analog circuit for use with the MOS transistors is mixed with the digital circuit. As a result, there is the problem that the chip area needs to be increased.
In the second prior art example, since no switch circuit is used, no digital circuit is required for the switch circuit. Consequently, the chip area is reduced. However, when an attempt is made to adjust the gain over a wide range, difficulties are experienced in maintaining the operating points of the MOS transistors in a desired region, thus presenting a problem that the linearity is significantly degraded in the event of voltage/current conversion.